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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Hex Schmitt Inverter The MC74VHCT14A is an advanced high speed CMOS Schmitt inverter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. Pin configuration and function are the same as the MC74VHCT04A, but the inputs have hysteresis and, with its Schmitt trigger function, the VHCT14A can be used as a line receiver which will receive slow input signals. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS level output swings. The VHCT14A input structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. * * * * * * * * * * * High Speed: tPD = 5.5ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 2A (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8V; VIH = 2.0V Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 0.8V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 60 FETs or 15 Equivalent Gates MC74VHCT14A D SUFFIX 14-LEAD SOIC PACKAGE CASE 751A-03 DT SUFFIX 14-LEAD TSSOP PACKAGE CASE 948G-01 M SUFFIX 14-LEAD SOIC EIAJ PACKAGE CASE 965-01 ORDERING INFORMATION MC74VHCTXXAD MC74VHCTXXADT MC74VHCTXXAM SOIC TSSOP SOIC EIAJ FUNCTION TABLE Inputs Outputs Y H L LOGIC DIAGRAM A1 1 2 Y1 A L H A2 3 4 Y2 Pinout: 14-Lead Packages (Top View) A3 5 6 Y3 Y=A A4 9 8 Y4 VCC 14 A6 13 Y6 12 A5 11 Y5 10 A4 9 Y4 8 A5 11 10 Y5 1 Y6 A1 Y1 A2 Y2 A3 Y3 GND 2 3 4 5 6 7 A6 13 12 4/99 (c) Motorola, Inc. 1999 1 REV 0 II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I I I I I I IIIIIIIII I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIII I I I I II I I I I I I I I IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIII IIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIII I I IIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIIIIIIII IIIIIIII I I II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIII IIIIIIII I I II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I II IIIIIIIII I I I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIII I I II I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I II I I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII I I I III I III IIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII I I I III I I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating -- SOIC Packages: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C II I I IIIIIIIIIIIIIIIIIIIIIII I I I I I I III I I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII MC74VHCT14A MAXIMUM RATINGS* Symbol VCC Vout Tstg ICC IOK Iout Vin PD IIK Storage Temperature Power Dissipation in Still Air, DC Supply Current, VCC and GND Pins DC Output Current, per Pin Output Diode Current Input Diode Current DC Output Voltage DC Input Voltage DC Supply Voltage Parameter SOIC Packages TSSOP Package - 0.5 to VCC + 0.5 - 65 to + 150 - 0.5 to + 7.0 - 0.5 to + 7.0 Value - 20 50 25 20 500 450 Unit mW mA mA mA mA DC ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS MOTOROLA Symbol S bl Symbol ICCT IOPD VOH VOL VT- ICC VCC Vout VH IIN Vin TA VT+IIIIIIII Positive Threshold Voltage Output Leakage Current Quiescent Supply Current Maximum Quiescent Supply Current Maximum Input Leakage Current Maximum Low-Level Output Voltage Minimum High-Level Output Voltage IOH = -50A Hysteresis Voltage Negative Threshold Voltage Operating Temperature, All Package Types DC Output Voltage DC Input Voltage DC Supply Voltage Parameter P Parameter IOL = 4mA IOL = 8mA VIN = 5.5V or GND IOH = - 4mA IOH = - 8mA VIN = VIH or VIL IOL = 50A VOUT = 5.5V Input: VIN = 3.4V VIN = VCC or GND VIN = VIH or VIL IOH = - 50A Test C di i T Conditions 0 to 5.5 VCC V 0.0 5.5 5.5 4.5 5.5 2.0 3.0 4.5 4.5 5.5 2.0 3.0 4.5 3.0 4.5 5.5 3.0 4.5 6.0 3.0 4.5 5.5 2 - 40 Min 4.5 0 0 2.58 3.94 0.30 0.40 0.50 0.35 0.5 0.6 Min 1.9 2.9 4.4 VCC + 85 Max 5.5 5.5 TA = 25C Typ 0.0 0.0 0.0 2.0 3.0 4.5 Unit _C _C V V V V V V 0.1 1.35 0.36 0.36 1.20 1.40 1.60 Max 0.5 2.0 0.1 0.1 0.1 1.7 2.0 2.0 2.48 3.80 0.30 0.40 0.50 0.35 0.5 0.6 Min 1.9 2.9 4.4 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. TA 85C VHC Data - Advanced CMOS Logic DL203 -- Rev 1 1.0 1.50 0.44 0.44 1.20 1.40 1.60 Max 0.1 0.1 0.1 1.6 2.0 2.0 20 5.0 v 2.34 3.66 0.30 0.40 0.50 0.35 0.5 0.6 Min TA 125C 1.9 2.9 4.4 1.0 1.65 0.52 0.52 1.20 1.40 1.60 Max 0.1 0.1 0.1 1.6 2.0 2.0 40 10 v Unit Ui mA A A V V V V V A MC74VHCT14A I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I IIIIIIII IIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I II I I I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) Symbol S bl tPLH, tPHL Parameter P Test C di i T Conditions TA = 25C Typ TA 85C TA 125C Min Max Min 1.0 1.0 1.0 1.0 Max Min 1.0 1.0 1.0 1.0 Max Unit Ui ns Maximum Propagation Delay, A to Y VCC = 3.3 0.3 V VCC = 5.0 0.5 V CL = 15pF CL = 50pF CL = 15pF CL = 50pF 8.3 10.8 5.5 7.0 4 12.8 16.3 15.0 18.5 10.0 12.0 10 17.0 20.5 8.6 10.6 10 11.5 13.5 10 CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 5.0 V CPD Power Dissipation C P Di i i Capacitance (N i (Note 1 ) 1.) pF F 21 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 6 (per buffer). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0 V) TA = 25C Symbol S bl VOLP VOLV VIHD VILD Characteristic Ch ii Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage 3.0V A 1.5V GND tPLH Y 1.5V VOL * Includes all probe and jig capacitance tPHL VOH DEVICE UNDER TEST OUTPUT CL* Typ 0.4 - 0.4 Max 0.8 - 0.8 3.5 1.5 TEST POINT Unit Ui V V V V Figure 1. Switching Waveforms Figure 2. Test Circuit (a) A Schmitt-Trigger Squares Up Inputs With Slow Rise and Fall Times VH Vin VCC VT+ VT- GND VOH Vout VOL Vout Vin VH (b) A Schmitt-Trigger Offers Maximum Noise Immunity VCC VT+ VT- GND VOH VOL Figure 3. Typical Schmitt-Trigger Applications VHC Data - Advanced CMOS Logic DL203 -- Rev 1 3 MOTOROLA MC74VHCT14A OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F -A- 14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -B- 1 7 P 7 PL 0.25 (0.010) M B M G C R X 45 F SEATING PLANE D 14 PL K M M B S J 0.25 (0.010) T A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019 MOTOROLA 4 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHCT14A OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ 0.10 (0.004) 0.15 (0.006) T U S M TU S V S N 2X L/2 14 8 0.25 (0.010) M L PIN 1 IDENT. 1 7 B -U- N F DETAIL E K K1 J J1 0.15 (0.006) T U S SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E VHC Data - Advanced CMOS Logic DL203 -- Rev 1 5 CCC EEE CCC EEE CCC A -V- MOTOROLA MC74VHCT14A OUTLINE DIMENSIONS M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965-01 ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 14 8 LE Q1 E HE M_ L DETAIL P 1 7 Z D e A VIEW P c b 0.13 (0.005) M A1 0.10 (0.004) MOTOROLA 6 VHC Data - Advanced CMOS Logic DL203 -- Rev 1 MC74VHCT14A NOTES VHC Data - Advanced CMOS Logic DL203 -- Rev 1 7 MOTOROLA MC74VHCT14A Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. - http://sps.motorola.com/mfax/ 852-26629298 HOME PAGE: http://motorola.com/sps/ JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488 MOTOROLA 8 MC74VHCT14A/D VHC Data - Advanced CMOS Logic DL203 -- Rev 1 |
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